Advanced video object generator

ABSTRACT

A computer video image generating system including a computer memory having three dimensional object data stored therein employs an advanced object generator for retrieving and processing the object data for output to a span processor for controlling the pixel-by-pixel video output signal for a video display. The advanced object generator includes a translucency processor, an edge-on fading processor, a level of detail blending processor and a bilinear interpolator for texture smoothing.

This application is a continuation of application Ser. No. 527,809,filed Aug. 30, 1983, now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to computer image generator (CIG) systems, and,more particularly, to an improved video object generator for use inreal-time imaging systems.

2. Description of the Prior Art

Simulators are being specified for a variety of training tasks otherthan the traditional tasks such as takeoff and landing, andair-to-ground weapons delivery. For some of these new tasks currentlevels of scene realism will not suffice. For example, a requirement ofnap of the earth helicopter pilot training is that the pilot start atsome distance from a tree or other obstacle, that he fly to a point onemeter from the tree as measured by the distance from the tip of hisrotor blades to the tree, and that he maintain that position. Arealistic image of the tree must be produced for the pilot toeffectively train for a flight requirement of this type. Prior artsystems were unable to generate an adequately detailed image in realtime for such applications.

One prior art system is disclosed in U.S. Pat. No. 4,343,037, issuedAug. 3, 1982 to Bolton and assigned to Redifon Simulation Limited. Inthis patent disclosure, columns 13-21, a texture pattern is stored inmemory and retrieved for each pixel along each scan line. As stated inthe patent, memory size and access time limitations limit the detailwhich can be handled by the system.

In depicting images of very complex objects, such as trees, the numberof edges and texture patterns required to generate a realistic imagewould be prohibitively large for a real-time system.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a computer imagegeneration system capable of generating complex objects in real-time fordisplay on video displays.

Another object of the present invention is to provide a CIG system forgenerating realistic images of three dimensional objects for real-timevideo display.

A more specific object of the present invention is the application ofcell texturing, level of detail blending, translucency modulation,bilinear interpolation smoothing and edge-on fading to real-time CIGsystems.

Accordingly, the advanced video object generator of the presentinvention includes a memory for storing data applicable to each cell ofa surface defining texture patterns or actual objects, translucency codecalculation boards, memory for storing a transparency or translucencycode and supplying this code on a pixel-by-pixel basis to the imagegenerator, level of detail calculators and level of detail blending,edge-on fading, and texture smoothing for generating images of threedimensional objects for computer image generation.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the invention believed to be novel and unobvious overthe prior art are set forth with particularity in the appended claims.The invention itself, however, as to organization, method of operation,and best mode contemplated by the inventor, together with furtherobjects and advantages, may best be understood by reference to thefollowing description taken in conjunction with the accompanyingdrawings, in which like reference characters refer to like elementsthroughout, and in which:

FIG. 1 is a schematic diagram illustrating the mapping of a scan line ofpixels onto a cell-textured face;

FIG. 2 is a schematic diagram illustrating the orientation of a set ofplanes upon which an image of a three-dimensional object is projectedfor use in computer generation of the object for video display by theobject generator of the present invention;

FIGS. 3A and 3B are a functional block diagram illustrating thefunctions performed by the advanced object generator of the presentinvention.

FIGS. 4, 5, 6 and 7 are schematic block diagrams illustrating the boardsfor calculating pixel coordinates relative to the cell textured faces;

FIG. 8 is a schematic block diagram illustrating the verticalinterpolator board of the present invention;

FIG. 9 is a schematic block diagram illustrating the horizontalinterpolator of the present invention;

FIG. 10 is a schematic block diagram illustrating the board forcalculating the maximum pattern gradient change in the image generatorof the present invention;

FIGS. 11A and 11B are a schematic block diagram illustrating the levelof detail calculator of the present invention;

FIG. 12 is a schematic block diagram illustrating the cell map addresscalculator of the present invention;

FIG. 13 is a schematic block diagram illustrating the cell smoothingfunction of the present invention;

FIG. 14 is a schematic block diagram illustrating the cell blendingfunction of the present invention;

FIG. 15 is a schematic block diagram illustrating thetranslucency/modulation Transform calculation for the present invention;

FIG. 16 is a schematic block diagram illustrating the cell texturetranslucency control function of the present invention; and

FIGS. 17-20 are photographs showing the image effects of the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention employs cell texture as one concept for thegeneration of images by computer image generation. Any point on adefined surface in 3-dimensional space can be specified by the values oftwo parameters. On a planar surface these parameters might be labeled xand y. Points on a cylindrical surface might be designated by values ofz and θ, and points on a sphere or ellipsoid can be defined by θ and φ.In the present specification we will use Q₁ and Q₂ as generic parameterdesignations.

FIG. 1 is a view of a planar surface with values of Q₁ and Q₂ shown.Base color or modulation information can be considered as functions ofQ₁ and Q₂. The functional relationship may involve quantitativeprocessing of the values of Q₁ and Q₂, it may involve using Q₁ and Q₂either separately or concatenated as addresses to a table-look-upmemory, or it may involve a combination of these techniques. In thesimplest form of operation, assume the integral portions of values of Q₁and Q₂ are combined and used as an address for elements of the diagram.This will provide a distinct address for each of the small squares inFIG. 1, referred to hereinafter as cells.

FIG. 1 also shows the images of a group of pixels on a scan line 30projected onto the face 32 containing the cells 34. In one mode ofoperation of cell texture, the values of Q₁ and Q₂ corresponding to thecenter of each pixel are determined, the modulation or color informationdesignated by this Q₁ -Q₂ combination is extracted from a computermemory previously loaded with the modulation or color information foreach face of a set of objects to be shown on a video display, and thesevalues are used to determine or modify the pixel video. The memorycontents can be determined by some algorithm applied to the Q₁ -Q₂values on the image of an object to be loaded into memory, by digitizingphotographs of features of regions to be represented, or by somecombination of these techniques. The results of these image describingtechniques are then stored in memory for retrieval and use in computerimage generation. The treatment of object images in this way forcomputer image generation, CIG, is called cell texturing.

The mathematics to determine the strike-point of a view ray on aparametrically defined curved surface is sufficiently complex that largeamounts of hardware are required to apply cell texture to such surfacesin real-time systems. For planar surfaces the values of Q expressed interms of view window location I, J is in the form: ##EQU1## in whichP_(o) and C₁ -C₆ are supplied from the vector processor, which generatesthe values of the coefficients for mapping video information from cellsonto pixels on the scene to be displayed. P_(o) is the reference valuewhich, in combination with C₁ -C₆, determines the location on a facestruck by a ray through pixel I, J. There is a separate set of P_(o) andC₁ -C₃ for each parameter, i.e., two sets for cell texture--one for Q1and the other for Q2. C₄ -C₆ are the same for both.

The numerator and denominator of the quotient in Equation 1 are eachlinear in I and J and hence easily updated by incrementing. This stillleaves the rather formidable task of obtaining the high precisionquotient for each pixel or subpixel.

Successful work with cell texture has been done with parameterscarefully adjusted so both pixels and texture cells are small relativeto the resolution of the eye, with on the order or two or three pixelsper cell. When a cell textured object on a video image recedes from theviewer, the cells decrease in size relative to the pixels. When the twoentities are comparable in size, moire effects result, which areparticularly distracting in scenes which change dynamically. If the celltextured face changes in orientation to become edge-on to the viewer,the cells decrease in size in one dimension leading to moire effects.If, in addition, a set of cell textured planar faces is being used tosimulate a feature with a shape other than that spatially defined by thefaces, distortion of the desired image can result as the face approachesan edge-on configuration. The present invention provides means forovercoming these difficulties of cell textured image generation.

In many applications, such as the simulation of trees, it is desiredthat the boundary of a textured surface in a computer generated image behighly irregular, and even have regions interior to the boundary of asurface where one can see through the feature represented by thetextured surface. While theoretically this could be achieved by definingthe boundary and interior holes with edges, it would require so large anumber of edges that processing for computer image generation isimpractical for real-time systems. The present invention providespractical apparatus capable of handling, in a real-time computer imagegeneration system, a realistic image of a feature having a veryirregular boundary and having holes interior to the feature boundary.

Some applications of cell texture involve tiling a large area withrepetitions of one or a small number of individual tile patterns. Inorder to provide a realistic image it is essential that there be noperceived indication of this tiling. Therefore, a technique is requiredto eliminate any indication of the tile boundaries in the scene. Thepresent invention uses a tile blending technique for illustrating largeareas without producing visible tile boundaries in the video image.

To illustrate the technique of the present invention a computergenerated image of a tree will be employed, because it is felt thatgeneration of realistic trees represents a high level of imagecomplexity, and the capability of producing realistic trees is essentialfor training applications in which operation of aircraft, such ashelicopters, in close proximity to objects, such as trees, is required.

One form of imaging model 40 used to generate images of threedimensional objects consists of a set of faces 42, 44, 46, 48, 50 and 52radiating like fins from a common axis 54 as shown in FIG. 2. Thisarrangement gives the appearance from all horizontal directions ofhaving a face close to perpendicular to the viewray, which is the linefrom the observer's eye to the object being displayed. The tree image isstored as texture cells projected onto the six faces as shown in FIG. 2,and retrieved or displayed to the viewer as required by the imagegenerator in response to inputs from the viewer controls. The storing ofthe image data in this manner, and the calculation of coordinates foruser orientation are performed by hardware outside the advanced objectgenerator of the present invention.

One significant modification of cell texture that led to the presentinvention was the concept of a transparency code. One word from the cellmemory, for example, all zeros, is interpreted not in a quantitativemanner, but as designating that cell as transparent. This makes itpossible for the outline of a feature to differ from the outline of theface on which cell texture defines the feature, since the cells aroundthe boundary of the face can be coded as transparent. It also makes itpossible to have open regions inside the face boundary, for example,inside the boundary of a tree, and, if a vehicle or other object lies onthe face behind the tree, it will be seen through these holes. Thiscapability can be used to illustrate features with extremely irregularboundaries such as trees, or to illustrate features having essentiallyrectangular faces, such as a vehicle, by coding the portion of the faceoutside the boundary of the vehicle as transparent. The tree imagesshown in the photograph of FIG. 17 show the effect of the use of atransparency code.

VARIABLE TRANSLUCENCE

Another key element of the present invention is the concept of variabletranslucence. Consider a cell near the boundary of a tree which is halfcovered by a tree leaf, and half covered by the sky. Straightdigitization of this cell will designate this cell as very light green.This will be acceptable when the cell is seen as against the sky, but asthe viewer moves it may be that the leaf will be seen against anothertree or against the ground. Then, unless a color change occurs, the treewill have an unnatural light halo. With the concept of translucency thetree leaf cell is designated standard tree green, with 50% translucency,i.e., only half the color content of the cell will be the green of thetree. When seen against the sky the cell will be a very light blue greencalled for at the boundary, since half the color of the cell will be skyblue. When seen against the ground, the cell will be a darkbrownish-green representing the combination of the standard tree greenwith 50% translucency and the background earth color. Variabletranslucency also allows the depiction of other visual effects, such assmoke which can range from opaque to barely visible.

EDGE-ON FADING

As described above, when viewing faces as they approach edge-onorientation, distracting and unrealistic effects are produced byunrefined cell texture techniques. The present invention provides atechnique for overcoming this problem by adding edge-on fading to theimage processing. As the angle between a plane of the face as shown inFIG. 2 and the viewray decreases, the entire face is gradually processedas translucent. The saturation decreases with angle until at some finalangle the face is completely transparent and is no longer processed. Ina dynamic test sequence it was determined that by starting the fading ata viewing angle of 36° and eliminating the face at 18° a realistic imagewith no artifacts of the edge-on fading is produced. Other angles arealso useable so long as the fading is done in such a way that the userperceives no artifacts. This provides for a gradual elimination of theface from the image as it approaches edge-on orientation, so that thedistracting and unrealistic effects of viewing the image at the edge-onorientation are eliminated. FIGS. 17 and 18 illustrate the image effectof edge-on fading. In FIG. 17 no edge-on plane appears but in FIG. 18the planes 49 appear clearly. These faces 49 detract significantly fromthe realism of the tree image.

LEVEL OF DETAIL

Another key feature of the present invention is level of detailprocessing. When the distance to a cell textured face is such that acell is approximately equal to a pixel in size, scintillation and moireeffects may result. The present invention overcomes this problem bycontrolling the size of cells relative to pixel size in each lineardimension. One particular embodiment of the present invention provides aset of nine levels of detail (LODs) which range from the highest levelof detail (LOD 0) containing 256×256 cells, with the linear dimension ofeach cell as 0.125 ft. and the lowest level of detail (LOD 9) being asingle value for the map. Table 1 shows a typical set of levels ofdetail and their respective cell sizes as used in one particular exampleof the present invention; these are exemplary only and the cell sizescan be selected by the user to any desired dimension.

                  TABLE 1                                                         ______________________________________                                        LOD 0 =    256 × 256 cells, each 0.125 feet per cell                    LOD 1 =    128 × 128 cells, each 0.250 feet per cell                    LOD 2 =    64 × 64 cells, each 0.500 feet per cell                      LOD 3 =    32 × 32 cells, each 1.000 feet per cell                      LOD 4 =    16 × 16 cells, each 2.000 feet per cell                      LOD 5 =    8 × 8 cells, each 4.000 feet per cell                        LOD 6 =    4 × 4 cells, each 8.000 feet per cell                        LOD 7 =    2 × 2 cells, each 16.000 feet per cell                       LOD 8 =    1 × 1 cells, each 32.000 feet per cell                       LOD 9 =    invisible (too far away)                                           ______________________________________                                    

LOD 8 with cells 32 ft. square may seem of such size as to bemeaningless, but this LOD is used for imaging faces of objects shown atdistances from the viewer such that a cell encloses only one or twopixels, and a face contains only a few cells, and greater detail at thatdistance could not be seen even if it were defined by the imagegenerator.

Transitions from one LOD to another are made at a distance from theviewer such that they would be barely discernible. However, the natureof the human perception system is such that even very slight differencesare noticeable if they occur abruptly. The present invention overcomesthis difficulty by using LOD blending, which is a gradual transitionfrom one LOD to the next. The computation to select the LOD to be usedfor any span on a display gives a whole number term and a fractionalterm. The fractional term is referred to as the alpha term. Itdesignates the portions of each of two adjacent levels of detail to beused in the blending process; hence, this process is referred to as LODalpha blending.

The effect of using this LOD transition technique is illustrated in thephotograph in FIG. 17. The sequence shows trees at increasing distances,and hence covers a number of LODs with a variety of alpha values. Yet,as will be recognized, the desired effect of LOD alpha blending, i.e.,gradual change in the image detail shown, is well illustrated. The tree41 is shown with substantially more detail than tree 43, but the pointof LOD transistion is not discernible. This same realism is also presentin dynamic sequences with no hint of scintillation or LOD transition.

CELL SMOOTHING

At the boundaries of image cells some smoothing technique must be usedto minimize the appearance of the edge of the cell within the image ofthe object shown. Consider a pixel somewhat smaller than a cell, e.g.,pixel 36 as shown in FIG. 1. As pixel 36 moves across a given cell,e.g., cell 38, the pixel is given the intensity of that cell. As pixel36 crosses the boundary to the next cell 39, it changes to the intensityof that next cell 39, and retains that intensity as it moves across thecell. Texture cell smoothing in the present invention provides a gradualtransition as described below. Assume a pixel with its center coincidentwith the center of a cell. The pixel will be given the intensity of thatcell. If the pixel starts moving parallel with a line of cells to theright toward an adjacent cell, it is given an intensity which is acombination of the two cells, even when the pixel is entirely containedwithin the first cell. The intensity will be changed gradually as thepixel approaches the cell boundary, and when the pixel reaches thecenter of the second cell it will have that cell's intensity. In atwo-dimensional case, this is accomplished by bilinear interpolation.The four cells whose centers define a polygon containing the center of apixel are identified. The pixel intensity is computed from the four-cellintensity values with a weighting based on the location of the pixelcenter relative to the cell centers. This technique eliminates theproblem of texture cell boundaries causing distracting artifacts fromthe image projected dynamically. The effect is shown in FIGS. 19 and 20.In FIG. 19 using area times color processing, the cells 45 of the imageare quite readily visible. In FIG. 20 using bilinear interpolation evenat a very close approach as shown at 47, the cells can not be seen.

TILE BLENDING

When a rectangular cell map of limited size is replicated to cover anextended surface, in either one or two dimensions, the process isreferred to as "tiling". Thus the right boundary of the map will abut acopy of the left boundary, and the bottom boundary will abut a copy ofthe top boundary. Interior to the map the cells represent samples of acontinuum, so cell-to-cell contrast is low and there is very limitedhigh spatial frequency content. When the boundaries abut as describedabove there will in general be regions of high contrast and high spatialfrequency content. The boundaries will be obvious on the tiled surface,giving an artificial appearance.

This problem is solved by adjusting the cell map contents to providefiltering at the boundaries. As an example, the rightmost cell of eachcell-row might be given a value equal to 55% of its original value plus45% of the value of the leftmost cell. The second cell from the rightwill be changed to 65% of its original value plus 35% of the value ofthe second cell from the left. Continuing, the fifth cell from the rightboundary will have 95% of its original value plus 5% of the value of thefifth cell from the left, and cells to the left of this will retaintheir original values. The same gradation is, of course, applied to agroup of cells along the left boundary. The result is a blending effectwhich makes the boundaries indistinguishable from other portions of theimage on the resulting display. If tiling is to be applied in twodimensions, similar blending is applied to the top and bottomboundaries. The actual size of the group of cells over which blending isapplied is adjusted to give best results for the specific contents ofeach map. In cases where there are extensive differences between twoabutting boundaries of a pattern, the interactive manual interventioncapability may be used to achieve best results.

HARDWARE BLOCK DIAGRAM

A block diagram of the advanced video object generator 100 of thepresent invention is shown in FIG. 3. Image data are input from vectorprocessor 102, and operator inputs are provided from the user controls(not shown). The image data contain color and texture information foreach object face in the scene to be displayed. The input data isreceived in input memories 104 for feeding to the advanced objectgenerator. The memories 104 are double buffered (or ping-ponged) in thedigital data base, so that the current field's worth of data may be readout, while the next field's data is being loaded into memories 104. Theinput memories 104 are made with sufficient depth (i.e., 4K) to hold allface data which may appear in one channel in a given field. Theconventional vector calculations which transform the patterncoefficients of the faces in a scene to the correct 3D perspective forthe observer's viewpoint are performed by the vector processor andsupplied to the advanced object generator. The viewpoint and operatorcontrol inputs are used to determine which object images are to beprocessed for display upon a particular video display. The presentinvention processes the image data for those objects determined to bevisible.

The boards 106-109 calculate the Q value defined by Equation 1. Afterthe Q values for each span corner of each span of a video scene arecalculated, a bilinear interpolation is used to determine Q values foreach individual pixel. The bilinear interpolation is performed by thecombination of vertical interpolators 110, 112, 114 and 116 andhorizontal interpolators 118 and 120. The outputs from the horizontalinterpolators are input to the cell map address boards 122, 124, 126 and128, which calculate map addresses for accessing the cell texture maps130, 132, 134 and 136. The cell texture maps contain cell texture datafor each cell of the image. The X and Y Q values are combined to formthe map address for each of the four cells whose centers form a polygonsurrounding the pixel center. The cell map shape can be selected to be1,024×64 cells, 512×128 cells or 256×256 cells with face control flags.Each map shape requires 64K memory data storage. Four copies of the mapare required to perform cell smoothing. The map LODS are used to controlthe map cell size relative to the display pixel size regardless of theviewray distance to the scene feature. Each different LOD map copy ismathematically generated by filtering the more detailed copy into a 1/4smaller map. Thus, a 256×256 map will become 128×128 and then a 64×64,etc. size map as view distance to the feature increases.

A total of 86K memory locations are required in the LOD cell memories130, 132, 134 and 136 to store all the different LOD versions of themaps. The map storage is arranged so that the N and N+1 LOD map versionsare available simultaneously to accomplish a smooth LOD transitionbetween the two levels. The determination of which LOD to use is made bymonitoring both the X and Y pattern gradients in the view plane. This iscontrolled by floating point subtraction hardware in the base numbercalculators 106-109. The worst case pattern change floating pointexponent selects which N and N+1 map LODs to use.

The outputs from the cell memories 130, 132, 134 and 136 are supplied tothe cell smoothing boards 138, 140, 142, 144. The cell smoothing boardsalso receive inputs from the horizontal interpolators which are used tocalculate the proportion of intensity input from the four cellssurrounding a given pixel. This calculation provides a coefficient foreach of the cell intensities for controlling the pixel intensity.

The four adjacent cells surrounding a view pixel are read from memoryand blended in cell smoothing boards 138, 140, 142 and 144 according tothe equation as follows: ##EQU2## where Mxy, Mxyl, Mxly, and Mxlyl arethe cell memory contents for the four cells surrounding the view panel.Each of the f numbers refers to the fractional bits. of the Q numberwhich remain after the LOD addressing shift. These bits are a directindication of the distances of the center of a view pixel to the centersof the four surrounding cells. Logic is included in the blendinghardware to control the cell smoothing at each of the four edges of thecell map. Each of the LOD N and LOD N+1 maps must be blended withseparate hardware. After the cell smoothing, the two different LODmodulations are blended together. This LOD blending is performed inboards 146, 148, 150, 152. Fractional gradient bits are used to form analpha LOD blend coefficient to combine the two LOD map versions asfollows:

    M=α*M(N+1)+(1-α)*M(N)                          Equation 3

At this point, the cell texture calculations have been completed. Thecell texture value is now transformed to control face translucency aswell as to modulate the face color by the translucency/modulation boards154, 156, 158, 160. The outputs from the translucency/modulation boardsare fed to the span processor 162 to control the image being generated.

The individual boards of a preferred embodiment of the advanced videoobject generator will now be described in detail. It should beunderstood that the bit counts shown on the Figures and describedhereinafter are selected for convenience and are not intended to belimiting. As shown in FIG. 4 the I, J calculator board 170 receives spanI 172 and span J 174 address data from the span processor. "Span I" and"Span J" are added to "increment I" 176 and "increment J" 178,respectively, by adders 180, 182 in order to compute the span address atthe four corners of the span. The resulting values are added to "Ioffset" 184 and "J offset" 186, respectively, by adders 188, 190 inorder to produce "ΔI" 192 and "ΔJ" 194 which are used in the computationof the Q value. In order to move to the center of a pixel, 0.5 must beadded to "ΔI" and "ΔJ". Hence a pullup 196 is used for the LSB. The I, Jcalculator board 170 receives standard data terminal bus input 198 whichis the test bus used with the system. The FPLA register 200 receivesstandard data terminal code input 202 to interface the user board to thestandard data terminal (SDT) word 204 to select one of sixteen testwords, a SDT read enable input 206 which is a control line coming fromthe SDT to indicate that the current test cycle is a read cycle, and aSDT write enable input 208 which is a control line coming from the SDTto indicate that the current test cycle is a write cycle. The "span I"input 172 provides the span I address from the span processor, and thespan J input 174 provides the span J address from the span processor. Aspan clock input 210 provides a clock signal in synchronism with thespan processor. The clock input 212 is provided from the systemreference clock. The span pulse inputs 214 are "enable" signals that areactive high during the total duration of the clock cycle to activate theboard for processing a particular span's data. It takes eight clockcycles to compute each span in the span processor. The cell texture basenumber calculator requires four clock cycles to compute the Q value atthe four corners of a span for pattern X, and four additional clockcycles to compute the Q value at the four corners of the span forpattern Y. The block diagrams show the sequence used in computing theeight Q values. The cell texture pattern values are calculated at eachincrement of the span in each eight clock cycle time.

The floating point dual multiplier and summer 220 shown in FIG. 5 isused to multiply two pairs of 22-bit floating point numbers,representing the face coefficients from the input memories by the deltaI and delta J outputs from the I, J calculator board 170. The tworesults 233, 239 are added to produce a 22-bit floating point number240. Thus, the arithmetic operation being implemented on this board isEquation 4 as follows:

    ADD OUT=(Xa * Ya)+(Xb * Yb)                                Equation 4

where all the variables are 22-bit floating point numbers. Themultiplier includes a 16-bit multiplier chip 222 that operates on thesignificand 221, 223 of the input variables. The exponents 225, 227 areadded using the adder 224. A second multiplier 226 is used to multiplythe significand of the input variables Xb 235 and Yb 237, and a secondadder adds the exponents of Xb and Yb. The outputs 233, 239 from themultiplier and adders are input to the floating point ALU chip 228 usedas a floating point adder. The output of the floating point adder 228 issupplied to a delay register 230 to be supplied as output 240 to thefloating point dual summer and multiplier 232, FIG. 6. The floatingpoint dual multiplier and summer receives span clock inputs to providetiming signals in synchronism with the span processor, and referenceclock inputs to control the operation of the multiplier and summer to bein synchronism with the reference clock. The TEST IN 234 and TEST OUT236 signals along with the FUNCTION SELECT input 238 test insert signalsare testing inputs and outputs to allow board testing during operationof the system, but have no direct effect upon the system operation.

The output 240 from the floating point dual multiplier and summer 220 issupplied to the floating point dual summer and multiplier 232, as shownin FIG. 6, as exponent 244 and significand 246 inputs. Adder 242 addsthe texture face start coefficients with the delta I and delta Jadjusted texture face coefficients to produce a 22-bit floating pointnumber. The A floating point adder 232 is used for the numeratorcalculation of Equation 1. The B floating point adder 241 is used forthe denominator calculation of Equation 1 and the output 243 is routedoff board to the reciprocal look-up table before being brought back tothe C add input 252, 258. The multiplier 248 multiplies the 16-bitsignificand inputs 250, 252 and adder 254 sums the 6-bit significandinputs 250, 252 and adder 254 sums the 6-bit exponents inputs 256, 258to yield Q of Equation 1 as a 23-bit output, which includes a 16-bitsignificand 260 and a 7-bit exponent 262.

The float-to-fixed calculator as shown in FIG. 7 converts the floatingpoint Q value 260, 262 provided from the floating point summer andmultiplier to a 24-bit fixed point number Q' 266. The floating point Qis connected to the Po summer hardware 274, which adds Po input 276 fromthe input memory to the Q' number 266. In order to meet the pipelinetiming requirements, the Po value is delayed through two holdingregisters 278, 280, where each holding register is equivalent to fourclock delays, so output 282 is in sync with the span processor. The chip284 stores the value of Q from the previous cycle and subtracts thepresent Q value from the previous Q value to generate a ΔQ value to beoutput at 286 for each 8 clock period cycle. This board also containsinput memory/output enable logic. This logic is divided into fivesections. The C2 and C3 memories are enabled during clock cycles 2, 3, 4and 5 for the X pattern, and during clock cycles 6, 7, 0 and 1 for the Ypattern. The Po memories are enabled during clock cycles 3, 4, 5 and 6for the X pattern and during clock cycles 7, 0, 1 and 2 for the Ypattern. The C1 memories are enabled during clock cycle 0, 1, 2 and 3for the X pattern and during clock cycles 4, 5, 6 and 7 for the Ypattern. The C4, C5 and C6 memories are enabled during all clock cycles.The C1 memory is tristated with the output of the floating point dualmultiplier and summer which generates the numerator of Equation 2, andthe C4 memory is tristated with the output of the floating point dualmultiplier and summer for generating the denominator of Equation 2.Therefore, the respective output enables are only active during thesecond half of each clock cycle.

The vertical interpolator 290 shown in FIG. 8 receives a 24-bit common Qinput 282 from the Po summer 274 shown in FIG. 7. At the start of thespan, Q top 292 is subtracted from Q bottom 294 by chip 296 and dividedby 4 at 298 and 300. Q-top 292 is stored in holding register 302. Theoutputs of registers 302 and 300 are added by adder 304 to yield a24-bit incrementing value to provide an offset for each increment of thespan. The output from register 302 is output as shown at 306 to adder308 which sums the Q-top value with the ADD IN input 310 from the matingvertical interpolator board's incrementer (not shown). The sum isdivided by two at 312 to provide an output which is tristated with theoutput from register 302 as shown at 314 to produce a Q-vert addressoutput 316. A set of X-left, X-right, Y-left and Y-right verticalinterpolator boards is required for the system. One set of boards isreferred to as the left vertical interpolator, and the other set isreferred to as the right vertical interpolator. The input to each of theboards will be loaded in the span processing time period prior to thespan being output. The X-left board will receive Qij as the Q top leftvalue and Qi8j as the Q bottom left value of a span. The X-right boardwill receive Qij8 as the Q top right input and the Qi8j8 as the Q bottomright value. The X-left board contains an incrementer that will sequencethrough Qij, Qi2j, Qi4j, and Qi6j. The right board contains anincrementer that will be used to sequence Qij8, Qi2j8, Qi4j8 and Qi6j8.These incrementer sequences will be repeated every four clock periodsfor a total of two times for the span. The incrementer on each board isconnected to three places: an output adder, directly to an outputregister, and also to the backplane. The boards are connected on thebackplane so that the final board output will be sequenced as shown inTable 3.

                  TABLE 3                                                         ______________________________________                                        CLK           LEFT         RIGHT                                              ______________________________________                                        0             Qij          Qij4                                               1             Qi2j         Qi2j4                                              2             Qi4j         Qi4j4                                              3             Qi6j         Qi6j4                                              4             Qij4         Qij8                                               5             Qi2j4        Qi2j8                                              6             Qi4j4        Qi4j8                                              7             Qi6j4        Qi6j8                                              ______________________________________                                    

The board will provide a 23-bit output Q-vert 316 to the horizontalinterpolator.

The horizontal interpolator 320 as shown in FIG. 9 functions to computethe three intermediate pixel Q values, given the Q value at the leftside of the span input 316 from the vertical interpolator board 290 andthe Q value at the right side of the input 318 from the matinginterpolator board. The inputs 316, 318 are summed by adder 322 and thesum 324 divided by two at 326 to yield the Q value for the horizontalmidpoint 328 between Q-left and Q-right. These steps are repeated byadders 330, 332 and dividers 334, 336 to yield the addresses 338, 340which are respectively the one-fourth and three-fourths addresses in thespan being processed. There are two horizontal interpolator boards, onefor the X pattern and one for the Y pattern. The Q left input 316provides the Q value for the left side of the span input from thevertical interpolator, and the Q right input 318 provides the Q value atthe right side of the span input from the vertical interpolator board.The horizontal interpolator 320 calculates three intermediate pixelvalues which yield a cell map address for accessing the texture mapmemory for each pixel in the cell.

The ΔQ Max calculator board 350 as shown in FIG. 10 is used to determinethe maximum pattern gradient change for use in calculating cell textureLOD. The ΔQ inputs 352, 354 provide 6 bits of ΔQ exponent and 8 bits ofΔQ significand from the ΔQ calculator board, FIG. 7. The calculationbegins with the floating point ΔQ inputs 352, 354. This input isconverted at 356, 358 to sign magnitude form, so that comparisons may beperformed more efficiently. The X ΔQ's in the I and J directions arefirst clocked into A registers 360, 362 and B registers 364, 366 forcomparison by comparator 368. The larger of A or B is selected foraddition with 1/2 the smaller. The floating point add is set up bysubtracting the smaller exponent from the larger. The significands areloaded into registers 376, 378. In the next clock period, the smallersignificand is downshifted by the exponent difference plus oneadditional shift 380 to account for the 1/2 addition. The shiftedsmaller significand 382 is added to the larger significand 384 by adder386 during the same clock period. Provision is made for a carry bit 388to bump the reference (larger) exponent 390 by adder 392. A clampcircuit comprising gate 394 and register 396 is provided for theexponent to maintain the final exponent within a 5-bit range. The carry388 will be used to downshift the significand at multiplexer 396, sothat proper scaling is maintained. Board 350 provides three identicalcalculations to produce three distinct ΔQ Max outputs, the first ofwhich is the diagonal gradient for the X and Y patterns, which arelabeled ΔQX Max and ΔQY Max, respectively. The X and Y Max gradients arecombined to form an overall ΔQ Max which is the final output 400 fromthe board. The diagonal gradient is approximated from the orthogonal Iand J pattern gradients by taking the Max gradient plus 1/2 the smallergradient. All three calculations are efficiently performed in timesequence by the same hardware. The final calculated ΔQX Max is saved ina holding register 403 during clock period D. The calculation is thenrepeated to determine ΔQY Max. This calculation will be available infour additional clock periods. At the end of this time period, thecalculated values for ΔQX Max and ΔQY Max are tristated back through thesame hardware to calculate the overall ΔQ Max. The gradients aresequentially generated in an 8 clock span period. The ΔQ Max output 400provides an 11-bit output in floating point form with 5 bits of exponentand 6 bits of significand to the LOD/Alpha board to be used in the LODcalculation.

The LOD/alpha calculator board, FIG. 11 contains PROMs 404, 406, 408 forthe computation of the LOD N, LOD N+1, alpha, 1-alpha, X and Y subtract,X and Y N and N+1 shift codes and delay registers 460, 466, 474 for cellshape select, transform map select and map edge select flags. The ΔQ Maxinput 400 is an 11-bit input calculated by the ΔQ Max calculator board,FIG. 10, which represents an average of the maximum gradients of boththe X and Y pattern. The ΔQ Max is in floating point format with theexponent defined to be always positive. The cell shape input 416 is a2-bit control input from the input memory which defines the map shape.

The LOD is a 4-bit number which is used to shift the cell map addressfor selection of the proper map LOD. The LOD is calculated by PROM 404by first multiplying the floating point ΔQ Max input 400 by a scalingvalue presently defined to be 0.65 decimal. This fixed point constantwill adjust for the minimum allowable LOD cell size. The resultingexponent with the addition of +5 is supplied to holding register 410 andthe LOD number 412. An adder 414 provides an input to register 415 whichyields LOD N+1 418 as an output. The LOD is limited to a maximum valueof 8 and a minimum value of 0. Alpha 420 is defined to be the 2E-2through 2E-5 remaining fractional bit of the adjusted ΔQ Maxsignificand, and is supplied from PROM 404 to registers 422 and 424.These bits are a measure of the relative proximity between two differentLODs and are used to do the LOD map blending on the cell alpha blendboard described hereinafter. If the LOD maximum clamp is enabled, thenalpha will be set to all ones. If the LOD minimum clamp is enabled, thenalpha will be set to 0. The 1-α term 426 is generated by inverting the 4alpha bits by inverter 428 and supplied to register 430.

Three PROMs (Only one 406 is shown.) are used to generate 20 bits worthof the X and Y two's complement -0.5 subtract coefficients. These PROMsderive the equivalent positive exponent internally using the sameprocedure as the LOD PROMs. The subtract coefficient PROMs 406 also havethe 2-bit cell shape select control 416 as an input so that compensationfor cell map shape can be made. The PROMs 406 generate an 11-bit Xsubtract coefficient held in register 432 for output 436, and a 9-bit Ysubtract coefficient held in register 434 for output 438.

The X and Y shift controls 440, 442 are used for scaling the fractionalQ bit used for texture smoothing on the cell smoother board. The shiftcodes are similar to the LOD numbers except that a separate adjustmentis required for both the X and Y fractional Q's to compensate for thecell map shape. This PROM derives the equivalent positive exponentinternally using the same procedure as the LOD PROM. The PROM 408 alsohas the 2-bit cell shape select control 416 as an input so thatcompensation for cell map shape can be made. The equivalent positiveexponent and cell shape code are then used to generate the shift codes440, 442 stored in registers 444, 446, respectively. The X/Y shift codesfor the N+1 cell smoother boards are calculated by adding 1, as shown in452 and 454 to the N shift code values held in registers 456, 458. Thecell shape select input 416 (FIG. 11B) is derived by register 460 from acell shape input 462 from the vector processor. A translucencymodulation and edge flag input 464 is supplied to register 466 forholding in register 468 to be output as a translucency modulation andedge flag output 470 to the translucency modulation board to bedescribed hereinafter. A transform input 472 from the translucencymemory and the modulation memory is held in registers 474, 476 foroutput 478 to the translucency and modulation board.

The cell map address board 480 as shown in FIG. 12 is used to addressthe cell map memories. Two boards are required for each pixelcalculation, one for the level of detail N and one for the level ofdetail N+1. The cell map address board combines the X and Y Q values482, 484 to form one address for the cell memory. A -0.5 offset is alsoinserted to the Qx and Qy values, so that the correct four surroundingcells for the current pixel calculation are selected. This offset wouldnormally be subtracted after the address LOD shift, so that the LOD mapselection may be made by shifting a pattern of all "1s" and a "0" intothe most significant bit address portion. A cell shape select code isalso used to correct the shift operation and addressing to match the mapshape selected.

The cell map address board 480 receives an 11-bit input 482 from ahorizontal interpolator board which represents the Q value for the Xcomponent for the current pixel, and a 9-bit input 484 from thehorizontal interpolator board which represents the Q value for the Ycomponent for the current pixel. The cell map address board alsoreceives an 11-bit input 436 adjustment to obtain the -0.5 subtract forthe X input and a 9-bit input 438 adjustment to obtain the -0.5 subtractfor the Y input, both of which originate from the LOD/alpha calculatorboard. A 4-bit LOD input code 486 is supplied from the LOD calculatorboard to select the correct map level of detail. The LOD input code 486will be LOD N for the LOD N board and LOD N+1 for the LOD N+1 board. Thecell map address board also receives a 2-bit input code, CELL SHAPESELECT 488 which selects the map shape factor. This signal originatesfrom the input memory but is delayed to the proper register position.The registers 490 and 492 combine the Q values and the subtract valuesto form addresses supplied to shifters 502 and 504. The LOD input 486 isinput to register 494, and the 2-bit cell shape select input 488 isinput to register 496. The detectors 498 and 500 receive Qx and Qyvalues respectively from registers 490 and 492 and combine these valueswith the LOD input 486 and cell shape select input 488 to determine thepresence of the all ones condition. The cell map address board 480 alsoreceives a Mem1 select input 518 which will enable register 520 tooutput the Mem1 address 522 if set to a logic 1, and will enableregister 524 to output the Mem2 address 526 if set to a logic 0, and aclock-in signal from the system reference clock. Outputs from the cellmap address board include a MemA select 512, MemB select 516 to controlthe LOD N or LOD N+1 address to the A or B memory, a MemA select delayoutput 508 and MemB select delay output 510 to select the A or B memoryoutput using the 4-to-1 multiplexer on the cell smoother board as wellas the Mem1 address output 522 which is a 16-bit output addresstristated with the Mem2 address of the associated LOD mating board, anda Mem2 address output 526 which is a 16-bit output address tristatedwith the Mem2 address of the associated LOD mating board. The Mem1 andMem2 address outputs are used as the address to either the A or B cellmemories for the cell Map look-up and to enable the outputs called Out 1Select and Out 2 Select of the Cell Map. These lines are used to enableeither the 8 most significant bits or the 8 middle bits of the cell map.This combination forms a 32K portion of the cell map memory. The outputsfrom the cell map address board 480 also include an X EQ Max and Y EQMax output which will be set to a logic "1", if the correspondingaddress section is at the map-end address as indicated by inputs fromdetectors 498, 500, respectively. These signals are connected to thecell smoother board to be used for map boundary control.

                  TABLE 4                                                         ______________________________________                                        MAP                                                                           ADRS  LOD NUMBER                                                              BIT   0      1      2    3    4     5    6    7    8                          ______________________________________                                        2E13  X-2    0      1    1    1     1    1    1    1                          2E12  X-3    X-2    0    1    1     1    1    1    1                          2E11  X-4    X-3    X-2  0    1     1    1    1    1                          2E10  X-5    X-4    X-3  X-2  0     1    1    1    1                          2E9   X-6    X-5    X-4  X-3  X-2   0    1    1    1                          2E8   X-7    X-6    X-5  X-4  X-3   X-2  0    1    1                          2E7   X-8    X-7    X-6  X-5  X-4   X-3  X-2  0    1                          2E6   Y-1    Y-1    0    0    0     0    0    0    0                          2E5   Y-2    Y-2    Y-3  0    0     0    0    0    0                          2E4   Y-3    Y-3    Y-2  Y-1  0     0    0    0    0                          2E3   Y-4    Y-4    Y-3  Y-2  Y-1   0    0    0    0                          2E2   Y-5    Y-5    Y-4  Y-3  Y-2   Y-1  0    0    0                          2E1   Y-6    Y-6    Y-5  Y-4  Y-3   Y-2  Y-1  0    0                          2E0   Y-7    Y-7    Y-6  Y-5  Y-4   Y-3  Y-2  Y-1  0                          A/I   Y-8    X      X    X    X     X    X    X    X                          Map Size: 256 × 256                                                     Cell Shape (2E1,2E0): 00                                                      ______________________________________                                    

                  TABLE 5                                                         ______________________________________                                        MAP                                                                           ADRS  LOD NUMBER                                                              BIT   0      1      2    3    4    5    6    7    89                          ______________________________________                                        2E13  X-2    0      1    1    1    1    1    1    11                          2E12  X-3    X-2    0    1    1    1    1    1    11                          2E11  X-4    X-3    X-2  0    1    1    1    1    11                          2E10  X-5    X-4    X-3  X-2  0    1    1    1    11                          2E9   X-6    X-5    X-4  X-3  X-2  0    1    1    11                          2E8   X-7    X-6    X-5  X-4  X-3  X-2  0    1    11                          2E7   X-8    X-7    X-6  X-5  X-4  X-3  X-2  0    11                          2E6   X-9    X-8    X-7  X-6  X-5  X-4  X-3  X-2  01                          2E5   Y-1    Y-1    0    0    0    0    0    0    00                          2E4   Y-2    Y-2    Y-1  0    0    0    0    0    00                          2E3   Y-3    Y-3    Y-2  Y-1  0    0    0    0    00                          2E2   Y-4    Y-4    Y-3  Y-2  Y-1  0    0    0    00                          2E1   Y-5    Y-5    Y-3  Y-3  Y-2  Y-1  0    0    00                          2E0   Y-6    Y-6    Y-5  Y-4  Y-3  Y-2  Y-1  0    00                          A/I   Y-7    X      X    X    X    X    X    X    X  X                        Map Size: 512 × 128                                                     Cell Shape (2E1,2E0): 01                                                      ______________________________________                                    

                                      TABLE 6                                     __________________________________________________________________________    MAP                                                                           ADRS                                                                              LOD NUMBER                                                                BIT 0   1  2  3   4  5  6   7  8  9 10                                        __________________________________________________________________________    2E13                                                                              X-2 0  1  1   1  1  1   1  1  1 1                                         2E12                                                                              X-3 X-2                                                                              0  1   1  1  1   1  1  1 1                                         2E11                                                                              X-4 X-3                                                                              X-2                                                                              0   1  1  1   1  1  1 1                                         2E10                                                                              X-5 X-4                                                                              X-3                                                                              X-2 0  1  1   1  1  1 1                                         2E9 X-6 X-5                                                                              X-4                                                                              X-3 X-2                                                                              0  1   1  1  1 1                                         2E8 X-7 X-6                                                                              X-5                                                                              X-4 X-3                                                                              X-2                                                                              0   1  1  1 1                                         2E7 X-8 X-7                                                                              X-6                                                                              X-5 X-4                                                                              X-3                                                                              X-2 0  1  1 1                                         2E6 X-9 X-8                                                                              X-7                                                                              X-6 X-5                                                                              X-4                                                                              X-3 X-2                                                                              0  1 1                                         2E5  X-10                                                                             X-9                                                                              X-8                                                                              X-7 X-6                                                                              X-5                                                                              X-4 X-3                                                                              X-2                                                                              0 1                                         2E4 Y-1 Y-1                                                                              0  0   0  0  0   0  0  0 0                                         2E3 Y-2 Y-2                                                                              Y-1                                                                              0   0  0  0   0  0  0 0                                         2E2 Y-3 Y-3                                                                              Y-2                                                                              Y-1 0  0  0   0  0  0 0                                         2E1 Y-4 Y-4                                                                              Y-3                                                                              Y-2 Y-1                                                                              0  0   0  0  0 0                                         2E0 Y-5 Y-5                                                                              Y-4                                                                              Y-3 Y-2                                                                              Y-1                                                                              0   0  0  0 0                                         A/I Y-6 X  X  X   X  X  X   X  X  X X                                         Map Size: 1024 × 64                                                     Cell Shape (2E1,2E0): 10                                                      __________________________________________________________________________

The LOD shift operations are shown in Tables 4, 5 and 6 for three mapshapes. The X pattern is always defined to be the denser pattern and isused to form the most significant bits of the map address. The X msb bitis exclusive or'ed as shown at 514 with the LSB of the LOD code toobtain MemA/MemB select control signals 512, 516, respectively. The lsbof the Y pattern is only needed for LOD 0 and is used to form the output1, 2 select lines to the cell memory. Note the pattern of all "1s" and a"0" which is shifted in from the msb end of the address select of thedifferent map LODs.

The -0.5 subtract control before the shift is actually performed with anadd operation. The two's complement equivalent of the number to besubtracted is therefore supplied to the board. The patterns for the Xand Y substract inputs are shown in Tables 7, 8 and 9. These patternsare wired shifted on the backplane for the LOD N+1 board slot.

                                      TABLE 7                                     __________________________________________________________________________    ADDER                                                                              LOD NUMBER     ADDER                                                                              LOD NUMBER                                           INPUT                                                                              0 1 2 3  4 5 6 INPUT                                                                              0 1 2 3  4 5 6                                       __________________________________________________________________________    2E-1 1 1 1 1  1 1 1 2E-1 1 1 1 1  1 1 1                                       2E-2 1 1 1 1  1 1 1 2E-2 1 1 1 1  1 1 0                                       2E-3 1 1 1 1  1 1 1 2E-3 1 1 1 1  1 0 0                                       2E-4 1 1 1 1  1 1 1 2E-4 1 1 1 1  0 0 0                                       2E-5 1 1 1 1  1 1 1 2E-5 1 1 1 0  0 0 0                                       2E-6 1 1 1 1  1 1 0 2E-6 1 1 0 0  0 0 0                                       2E-7 1 1 1 1  1 0 0 2E-7 1 0 0 0  0 0 0                                       2E-8 1 1 1 1  0 0 0 2E-8 0 0 0 0  0 0 0                                       2E-9 1 1 1 0  0 0 0 2E-9 0 0 0 0  0 0 0                                       2E-10                                                                              1 1 0 0  0 0 0 Corresponding Y = 64 MAP                                  2E-11                                                                              1 0 0 0  0 0 0                                                           Map: X = 1024    for LOD N                                                    shift left one place for LOD N + 1                                            __________________________________________________________________________

                                      TABLE 8                                     __________________________________________________________________________    ADDER                                                                              LOD NUMBER      ADDER                                                                              LOD NUMBER                                          INPUT                                                                              0 1 2 3 4 5 6 7 INPUT                                                                              0 1 2 3 4 5 6 7                                     __________________________________________________________________________    2E-1 1 1 1 1 1 1 1 1 2E-1 1 1 1 1 1 1 1 1                                     2E-2 1 1 1 1 1 1 1 1 2E-2 1 1 1 1 1 1 1 0                                     2E-3 1 1 1 1 1 1 1 1 2E-3 1 1 1 1 1 1 0 0                                     2E-4 1 1 1 1 1 1 1 0 2E-4 1 1 1 1 1 0 0 0                                     2E-5 1 1 1 1 1 1 0 0 2E-5 1 1 1 1 0 0 0 0                                     2E-6 1 1 1 1 1 0 0 0 2E-6 1 1 1 0 0 0 0 0                                     2E-7 1 1 1 1 0 0 0 0 2E-7 1 1 0 0 0 0 0 0                                     2E-8 1 1 1 0 0 0 0 0 2E-8 1 0 0 0 0 0 0 0                                     2E-9 1 1 0 0 0 0 0 0 2E-9 0 0 0 0 0 0 0 0                                     2E-10                                                                              1 0 0 0 0 0 0 0 Corresponding Y = 128 MAP                                2E-11                                                                              0 0 0 0 0 0 0 0                                                          MAP: X = 512    for LOD N                                                     shift left one place for LOD N + 1                                            __________________________________________________________________________

                                      TABLE 9                                     __________________________________________________________________________    ADDER                                                                              LOD NUMBER        ADDER                                                                              LOD NUMBER                                        INPUT                                                                              0 1 2 3 4 5 6 7 8 INPUT                                                                              0 1 2 3 4 5 6 7 8                                 __________________________________________________________________________    2E-1 1 1 1 1 1 1 1 1 1 2E-1 1 1 1 1 1 1 1 1 1                                 2E-2 1 1 1 1 1 1 1 1 0 2E-2 1 1 1 1 1 1 1 1  0                                2E-3 1 1 1 1 1 1 1 0 0 2E-3 1 1 1 1 1 1 1 0  0                                2E-4 1 1 1 1 1 1 0 0 0 2E-4 1 1 1 1 1 1 0 0  0                                2E-5 1 1 1 1 1 0 0 0 0 2E-5 1 1 1 1 1 0 0 0  0                                2E-6 1 1 1 1 0 0 0 0 0 2E-6 1 1 1 1 0 0 0 0  0                                2E-7 1 1 1 0 0 0 0 0 0 2E-7 1 1 1 0 0 0 0 0  0                                2E-8 1 1 0 0 0 0 0 0 0 2E-8 1 1 0 0 0 0 0 0  0                                2E-9 1 0 0 0 0 0 0 0 0 2E-9 1 0 0 0 0 0 0 0  0                                2E-10                                                                              0 0 0 0 0 0 0 0 0 Corresponding Y = 256 MAP                              2E-11                                                                              0 0 0 0 0 0 0 0 0                                                        MAP: X = 256    for LOD N                                                     shift left one place for LOD N + 1                                            __________________________________________________________________________

A cell map is defined to be either 256×256, 512×128, or 1024×64. Themaps require a total storage of 86K nibbles (4 bits of word width foreach location). Each coarser map LOD requires a factor of four lessstorage; e.g., LOD 0 requires a 64K map memory, and LOD 1 requires a 16Kmap memory. The map storage must be arranged so that the computed mapLOD N and the rext coarser LOD N+1 are available simultaneously. Thisrequirement is satisfied by the breaking up the map storage intoseparate memories A and B as shown in Table 10. Note that memory A and Balternate lower and upper map portions depending upon which LOD is beingaddressed. This alternation is controlled on the board by tristatingeither the LOD N or LOD N+1 card output to the A or B memory boarddepending upon the LSB bit of the LOD number.

                  TABLE 10                                                        ______________________________________                                                                      TOTAL REQUIRED                                        (48K × 4)                                                                           (48K × 4)                                                                           STORAGE per                                     LOD   MEM A ADRS  MEM B ADRS  LOD LEVEL                                       ______________________________________                                        0        0 → 32,767                                                                      32,768 → 65,535                                                                    32K                                             1      8,192 → 16,383                                                                       0 → 8,191                                                                        8K                                             2        0 → 2,047                                                                       2,048 → 4,095                                                                       2K                                             3       512 → 1,023                                                                       0 → 511                                                                           512                                             4      0 → 127                                                                           128 → 255                                                                          128                                             5     32 → 63                                                                             0 → 31                                                                            32                                              6     0 → 7                                                                               8 → 15                                                                            8                                               7     2 → 3                                                                              0 → 1                                                                              2                                               8     1           1           1                                               ______________________________________                                    

In addition to the separate A and B storage requirement, cell smoothingrequires that four maps be available for each pixel. This is due to aneed to calculate a pixel intensity based upon smoothing between thefour cells whose centers form a polygon surrounding the pixel center.The four maps are designated XY, XY1, X1Y, and X1Y1. The LOD calculationcontrols the map cell to pixel size ratio.

Once a particular map for a LOD is computed, the address for the XY cellis obtained by subtracting 0.5 from the X and Y address components (seeTables 7, 8 and 9). The four maps are stored at the XY address, so thatall the maps will be available when only the XY address is supplied. Atotal of 43K nibble locations are required for each of the A and Bmemories.

The cell smoother board 540 as shown in FIG. 13 provides the blend ofthe four cells surrounding the pixel into an overall modulation whichreflects the relative distance of each cell center to the pixel center.The fractional values of the X and Y Q values are used as a directmeasure of the cell distance as follows: ##EQU3## This formula iscalculated with a PROM lookup table 542. The fractional Q values arefirst shifted for LOD adjustment before being routed to the PROM.Separate calculations are required for LOD N and LOD N+1 of each pixelposition, thus a total of 8 boards are required for the system. Theboard includes cell edge control 544 for processing cell edgeconditions. Provision is made for substitution of a translucency wordfrom the input memory as one of the cell edge control selections. A4-to-1 multiplexer 546 on the board selects memory A or memory B inputand selects either the 32K LOD 0 or 16K greater than LOD 0 map as aboard input.

The cell smoother board 540 receives as inputs: FX 548, 10-bits offractional input QX which originate from the horizontal interpolatorboard; FY 552, 12-bits of fractional input QY which originate from the Yhorizontal interpolator boards; an X shift 550 and Y shift 554 controlinputs which originate from the LOD/alpha calculation board. The celledge control 544 receives XY end flags 556-570 which originate from theinput memory to provide cell edge data to the board but are delayed tobe in synchronism with the inputs from the interpolator boards. Celledge control 544 receives X EQ Max 572 and Y EQ Max 574 input flagswhich are address top input flags, which originate from the cell mapaddress board. An X sign input 576 and a Y sign input 578 are providedas the Q sign bit input, and X or Y overflow inputs 580 from the sameboard provide Q overflow inputs to the cell edge control 544.Multiplexer 546 receives a set of four 16-bit inputs, MemA 32K 582, MemB32K 584, MemA 16K 586 and MemB 16K 588 from the cell memory boards as acontrol input for accessing the system memory. An LOD 0 flag 590 inputcontrols the selection of 32K memory only of the LOD N board. The memoryB select 592 input control originates from the cell map address boardand is connected to the MemB select signal for the LOD N+1 cardposition. Translucency is input in 4 input lines as shown at 594 whichcome from the input memory after being appropriately delayed, as shownat 596. The translucency threshold value is defined as the binary valuebeyond which complete transparency is to be forced. The multiplexers598, 600, 602, 604 selectively transmit modulations Mxy, Mxy1, Mx1y andMx1y1 or the translucency code to multipliers 606, 608, 610, 612,respectively. Inputs from the PROM lookup 542 are also input to themultipliers and the products are output to adders 614, 616 and 618 toproduce M out 620 as in Equation 6. The output from the board, M out, isan 8-bit output which adds four additional fractional bits obtaired byinterpolation from the four-bit cell values. A set of eight cellsmoother boards provides M out values to the cell α blend board.

A cell α blend board 630 as shown in FIG. 14 generates a smooth blendbetween cell map LOD N and LOD N+1, the next coarser level. The boardprocesses four pixels. The output modulation is calculated as follows:

    M=α*M(N+1)+(1-α)*M (N)                         Equation 6

The cell α blend board receives a set of M(N)X inputs 632, 634, 636, 638which is one of the four 8-bit modulatior inputs which originate fromthe LOD N map and a set of M(N+1) inputs 640, 642, 644, 646 which is oneof the four 8-bit modulation inputs from the LOD N+1 map. The cell αboard also receives an α input 648 which is a 4-bit fractional inputgenerated by the LOD α calculator board, and the (1-α) input 650 whichis a 4-bit 1's complement of α. The cell α blend function calculators652, 654, 656, 658 include multipliers 660, 662 which provide productoutputs to adder 664. The cell α blend board provides a plurality of8-bit modulation M(x) outputs 666, 668, 670, 672 which are supplied asinputs to the translucency modulation transform board.

The translucency/modulation transform cell/stripe select board 680 asshown in FIG. 15 is used to select between stripe texture or celltexture as the base modulation. Two transform maps 682, 684 are locatedon the board, one 682 for the translucency output 686 and one 684 forthe texture modulation output 688. The board input modulation isconnected to the address input to the maps, so that any desirablepattern transformation can be applied to the translucency and modulationseparately. If a map has the current address stored at each memorylocation, then no transformation will take place. Any desired deviationcan be applied starting from this basis. The translucency transform isused for programming the translucency threshold, slope and inverseselection where needed. The Cell Tex input 690 provides 8 input bits ofcell modulation from the α blend board 630, and the Stripe Tex input 692provides 8 input bits of stripe modulation from a conventional textureboard. The translucency map select input 694 provides a 4-bit input codedelayed from the input memory which selects one of 16 availabletranslation maps for the face being processed. The translate map selectinput 696 provides a 4-bit input code delayed from the input memorywhich selects one of 16 available translation maps for the face beingprocessed. The select stripe texture input 698 provides a control lineinput which also originates from the input memory, for controlling theselection of stripe texture. The translucency modulation is used tocontrol the pixel by pixel face translucency of a CIG object.

The translucency output 686 is provided to the translucency multiply andmask look-up board 700 as shown in FIG. 16. Board 700 includes amultiplier PROM 702 which multiplies the 6-bit translucency multiplier686 and a 6-bit control word 704 input from the Frame II memory 102.This multiplication yields a final pixel translucency percentage value706 which is output to PROMs 708, 710, 712 and 714, which also receive a5-bit control word 716 as inputs. PROMs 708, 710, 712 and 714 use thecontrol word 716 to select the desired filter subpixel mask pattern.Each mask consists of a plurality of bits stored at successive addressesin the PROMs. Each mask pattern differs from its adjacent mask patternsin the PROM by one bit more or one bit less. The PROMs 708, 710, 712 ard714 output 8-bit translucency mask values 718, 720, 722 and 724 viadelay registers 726 used to maintain proper output synchronism with thespan processor clock. The translucency mask values define the ratio ofthe combination of the colors of two faces according to Equation 7.

    C=T*C.sub.T +(1-T)*C.sub.B                                 Equation 7

in which C is the observed color of the displayed pixel, T is thetranslucency of the face, C_(T) is the translucent face color and C_(B)is the color behind the translucent face. For example, in a system with32 bit mask patterns, a face with 0/32 translucency is transparent, andtherefore has no effect on the color of the displayed pixel, while aface with 32/32 translucency is an opaque face which totally defines thecolor of the displayed pixel. In this fashion the edge-on fadingdescribed above can be accomplished by supplying as the input 704 afading factor dependent upon the viewing angle. A second translucencymultiply and mask look-up board is employed to process inputs from thespan processor, so that the two boards provide four pixel calculationpaths as required by the span processor. The outputs 718, 720, 722, 724and 730, 732, 734, 736 are provided to the span processor to control thepixel-by-pixel image displayed on the system video displays.

As will be appreciated by those skilled in the art, the presentinvention provides an advanced object generator capable of processingcomplex object images in real time with adequate detail to provide thevisual cues necessary for advanced simulator training missions.

What is claimed is:
 1. An advanced object generator comprising:data memory means for storing cell-by-cell data for each of a plurality of faces of a plurality of three-dimensional objects, said cell data including data stored for each three-dimensional object on a plurality of planes, said planes being arranged in such a manner as to respectively present a plurality of viewing angles relative to a given view point; vector processing means for calculating object transformations that translate operator inputs into image orientation control signals and for calculating pixel-by-pixel image data; means for receiving image data from said vector processing means for selecting image data projected from selected ones of said plurality of planes for processing or video display; edge-on fading factor processing means for calculating an edge-on fading factor for each face of said plurality of faces for each three-dimensional object to be displayed, each of said plurality of planes comprising a plurality of planes intersecting along a line within a respective object and said means for calculating an edge-on fading factor comprising:means for calculating a viewing angle between a viewray extending from said given viewpoint to an object being displayed and the respective planes of the object being displayed, and translucency threshold calculation means for providing a multiplier for each respective plane of a three-dimensional object, said multiplier being indicative of the size of said respective viewing angle for each plane of each object to be displayed; span processing means responsive to said edge-on fading factor processing means for calculating a fading factor percentage value based on the calculated edge-on fading factor for each face of said plurality of faces for each three-dimensional object of pixel-by-pixel display data; video monitor means for displaying images of said objects comprising pixel-by-pixel displays of said display data; and wherein said translucency threshold calculation means comprises: means for receiving viewing angle data for each respective face of an object from said means for calculating a viewing angle; means for comparing each said respective viewing angle with a predetermined minimum angle and a predetermined maximum angle; means for calculating a translucency coefficient for each said respective face when said viewing angle is between said minimum and said maximum viewing angles; means for making each said respective face completely transparent when said viewing angle is less than said minimum viewing angle; and means for supplying said respective translucency coefficient to said span processing means.
 2. The invention of claim 1 wherein said means for calculating a translucency coefficient comprises:means for calculating a translucency coefficient when a respective one of said viewing angles is less than 36 degrees and greater than 18 degrees.
 3. An advanced object generator comprising:object data memory means for storing cell-by-cell data for a plurality of levels of detail of a plurality of a plurality of faces of a plurality of three-dimensional objects for retrieval and processing for video display of such objects; vector processing means for translating operator inputs into image orientation control signals for calculating pixel-by-pixel display data; first level of detail calculation means for calculating address data to retrieve from said object data memory means data for a first level of detail for each object image to be processed for video display, said first level of detail calculation means comprising:means for calculating cell image size of each cell of a scene to be displayed; means for comparing said cell image size to a previously calculated pixel dimension in order to determine which levels of detail to process; means for accessing a first computer memory look-up table having previously determined level of detail data stored therein; second level of detail calculation means for calculating address data to retrieve from said object data memory means data for a second level of detail for each object image to be processed for video display, said second level of detail calculation means comprising:means for accessing a second computer memory look-up table having previously determined level of detail data stored therein; means for outputting cell data previously stored in computer map memory means for each of said first and second levels of detail for each object to be displayed, level of detail blending means for combining the data for said first level of detail and the data for said second level of detail into a single level of detail output for each pixel of an image of an object, wherein said level of blending means comprises; means for receiving as inputs gradients of image patterns upon each face image of a three-dimensional object; means for receiving as inputs gradients of image patterns upon each face image of a three-dimensional object; means for comparing said gradients with a predetermined maximum gradient for each of two dimensions; means for comparing said gradients with predetermined values of said gradients to determine said higher level of detail; means for calculating a level of detail blend control value; means for calculating the one's complement of said level of detail blend control output; means for multiplying said level of detail blend control value by said cell data for said first level of detail to generate a first product output; means for multiplying said one's complement of said blend control value by said cell data for said second level of detail to generate a second product output; summing means for adding the first product output to the second product output to produce a single modulation value output for each pixel of an image; span processing means for translating said level of detail output into pixel-by-pixel display data; and video monitor means for displaying a plurality of images of objects comprising pixel-by-pixel displays of said display data.
 4. The invention of claim 3 comprising:a plurality of said level of detail blending means each providing a level of detail modulation value output for a plurality of pixels of said image.
 5. An advanced object generator comprising:data memory means for storing cell-by-cell object data for each of one or more faces of a plurality of objects for retrieval and processing for video display of such objects; vector processing means for calculating object transformations that translate operator inputs into image orientation control signals and for calculating pixel-by-pixel image data; cell texture address means for determining a memory location to be accessed for retrieval of cell texture data from said data memory means for display, said cell texture address comprising:first and second floating point dual multiplying and summing means for calculating a first numerator and a second numerator needed for calculating object location coefficients for each object face to be displayed; floating point dual summing and multiplying means for calculating a denominator common to both said coefficients; means for calculating the reciprocal of said demoninator; means for multiplying said denominator reciprocal by said first numerator and said second numerator and for adding to the resulting products reference values of said respective first and second numerators to obtain addresses on an object face corresponding to a span corner; vertical interpolator means for calculating intermediate address parameters of image texture data of image elements disposed in one dimension between points located at addresses output by said floating point dual summing and multiplying means and for accessing texture data of predetermined columns of pixels on a span of said video display; horizontal interpolator means for calculating intermediate address parameters of image texture data of image elements disposed in a second dimension on lines between points on first and second ones of said columns of pixels; cell texture output means for outputting said cell texture data; and span processing means for translating said cell texture data into pixel-by-pixel displays of said display data,
 6. The invention of claim 5 further comprising bilinear interpolation means comprising:means for receiving a set of vertical and horizontal address pairs defining a span from said data memory means; means for calculating an incrementing value; incerementing means for incrementing a plurality of intermediate vertical addresses defining a plurality of pixel addresses separated vertically by said incrementing value along respective left and right hand columns of pixels defining respective edges of said span; means for calculating horizontal addresses for respective rows of pixels located between respective pairs of vertically aligned pixels of said left and right hand columns to define a complete array of pixel addresses for said span; and output means for accessing a texture map memory at each pixel address of said array of pixel addresses.
 7. The invention of claim 6 wherein said means for calculating an incrementing value comprises:means for subtracting a vertical address of a first pixel at one end of a column of pixels from a vertical address of a second pixel at the other end of said column of pixels to obtain a vertical address difference; and means for dividing said vertical address difference by a predetermined constant equal to a number of desired vertical increments in said column.
 8. The invention of claim 7 wherein said incrementing means comprises:adder means for repetitively adding said incrementing value to a first vertical address and outputting a new vertical address after each successive addition until said first vertical address equals a second vertical address.
 9. The invention of claim 8 wherein said means for calculating horizontal address values comprises:first horizontal address summing means for adding two horizontal addresses input from said data memory means; first divider means for dividing the sum of said horizontal addresses to yield a span horizontal midpoint address; second horizontal summing means for adding a first horizontal address from said data memory means and said horizontal midpoint address; second divider means for dividing the sum of said first horizontal address and said horizontal midpoint address to yield a one-fourth span horizontal address; third horizontal summing means for adding a second horizontal address from said data memory means and said horizontal midpoint address; and third divider means for dividing the sum of said second horizontal address and said horizontal midpoint address to yield a three-fourths span horizontal address.
 10. An advanced object generator for providing computer generated image control signals for real-time display comprising:data memory means for storing cell-by-cell data for a plurality of levels of detail for a plurality of faces of a plurality of three-dimensional objects for retrieval and computer processing for video display of such objects; said cell data including data stored for each three-dimensional object on a plurality of planes; said planes being arranged in such manner as to respectively present a plurality of viewing angles to a given viewpoint; vector processing means for calculating object transformations that translate operator inputs into image orientation control signals and for calculating valid pixel-by-pixel image data; translucency code storage means for storing predetermined translucency factors for selected cells of the object faces; translucency code processing means for calculating translucency factors on a pixel-by-pixel basis for said selected cells of an object; means for receiving image data from said vector processing means for selecting image data projected from selected ones of said plurality of planes for processing for video display; means for calculating an edge-on fading factor for each face of said plurality of faces for each three-dimensional object to be displayed; first level of detail calculation means for calculating address data to retrieve from said object data memory means data for a first level of detail for each object image to be processed for video display; second level of detail calculation means for calculating address data to retrieve from said object data memory means data for a second level of detail for each object image to be processed for video display; level of detail blending means for combining the data for said first level of detail with the data for said second level of detail into a single level of detail output for each pixel of a video image of an object; bilinear interpolation means for calculating pixel-by-pixel address data for each span to be processed; cell texture address means for determining a memory location in said data memory means to be accessed for retrieval of cell texture data; output means for outputting pixel-by-pixel image control data; span processing means for receiving said pixel-by-pixel image control data and translating said image control data into pixel-by-pixel display data; and video monitor means for displaying a plurality of images of objects comprising pixel-by-pixel displays of said display data.
 11. The invention of claim 10 wherein said translucency code processing means comprises:means for selecting one translucency map, from a plurality of translucency maps stored in said data memory means, for each of the object faces to be processed for display upon said video monitor means; and means for multiplying a translucency code for each pixel in an object retrieved from said one translucency map by cell data for each pixel of said object.
 12. The invention of claim 10 wherein each of said plurality of planes comprises a plurality of planes intersecting along a line within a respective object and said means for calculating an edge-on fading factor comprises:means for calculating a viewing angle between a viewray extending from said given viewpiont to an object being displayed and the respective planes of the object being displayed; and translucency threshold calculation means for providing a multiplier for each respective plane of a three-dimensional object, said multiplier being indicative of the size of said respective viewing angle for each plane of each object to be displayed.
 13. The invention of claim 12 wherein said translucency threshold calculation means comprises:means for receiving viewing angle data for each respective face of an object from said means for calculating a viewing angle; means for comparing each said respective viewing angle with a predetermined minimum angle and a predetermined maximum angle; means for calculating a translucency coefficient for each said respective face when said viewing angle is between said minimum and said maximum viewing angles; means for making each said respective face completely transparent when said viewing angle is less than said minimum viewing angle; and means for supplying said respective translucency coefficient to said span processing means.
 14. The invention of claim 13 wherein said means for calculating a translucency coefficient comprises:means for calculating a translucency coefficient when a respectively one of said viewing angles is less than 36 degrees and greater than 18 degrees.
 15. The invention of claim 14 wherein each said plurality of planes comprises:a plurality of planes intersecting along a line within a respective object.
 16. The invention of claim 10 wherein said first level of detail calculation means comprises:means for calculating cell image size of each cell of a scene to be displayed; means for comparing said cell image size to a previously calculated pixel dimension in order to determine which levels of detail to process; means for accessing a first computer memory lookup table having previously determined level of detail data stored therein; and wherein said second level of detail calculation means comprises: means for accessing a second computer memory look-up table having previously determined level of detail data stored therein; and means for outputting cell data previously stored in computer map memory means for each of said first and second levels of detail for each object to be displayed.
 17. The invention of claim 16 wherein said first level of detail comprises a higher level of detail than said second level of detail and said level of detail blending means comprises:means for receiving as inputs gradients of image patterns upon each face image of a three-dimensional object; means for comparing said gradients with a predetermined maximum gradient for each of two dimensions; means for comparing said gradients with predetermined values of said gradients to determine said higher level of detail; means for calculating a level of detail blend control value; means for calculating the one's complement of said level of detail blend control output; means for multiplying said level of detail blend control value by said cell data for said first level of detail to generate a first product output; means for multiplying said one's complement of said blend control value by said cell data for said second level of detail to generate a second product output; summing means for adding the first product output to the second product output to produce a single modulation value output for each pixel of an image.
 18. The invention of claim 17 comprising:a plurality of said level of detail blending means each providing a level of detail modulation value output for a plurality of pixels of said image.
 19. The invention of claim 10 wherein said cell texture address means comprises:first and second floating point dual multiplying and summing means for calculating a first numerator and a second numerator needed for calculating object location coefficients for each object face to be displayed; floating point dual summing and multiplying means for calculating a denominator common to both said coefficients; means for calculating the reciprocal of said denominator; and means for multiplying said denominator reciprocal by said first numerator and said second numerator and for adding to the resulting products reference values of said respective first and second numerators to obtain addrsses on an object face corresponding to a span corner; vertical interpolator means for calculating intermediate address parameters of image texture data of image elements disposed in one dimension between points located at addresses output by said floating point dual summing and multiplying means and for accessing texture data of predetermined columns of pixels on a span of said video display; and horizontal interpolator meana for calculating intermediate address parameters of image texture data of image elements disposed in a second dimension on lines between points on first and second ones of said columns of pixels.
 20. The invention of claim 19 wherein said bilinear interpolation means comprises:means for receiving a set of vertical and horizontal address pairs defining a span from said data memory means; means for calculating an incrementing value; incrementing means for incrementing a plurality of intermediate vertical addresses defining a plurality of pixel addresses separated vertically by said incrementing value along respective left and right hand columns of pixels defining respective edges of said spans; means for calculating horizontal addresses for respective rows of pixels located between respective pairs of vertically aligned pixels of said left and right hand columns to define a complete array of pixel addresses for said span; and output means for accessing a texture map memory at each pixel address of said array of pixel addresses.
 21. The invention of claim 20 wherein said means for calculating an incrementing value comprisesmeans for subtracting a vertical address of a first pixel at one end of a column of pixels from a vertical address of a second pixel at the other end of said column of pixels to obtain a vertical address difference; and means for dividing said vertical address difference by a predetermined constant equal to a number of desired vertical increments in said column.
 22. The invention of claim 21 wherein said incrementing means comprises:adder means for repetitively adding said incrementing value to a first vertical address and outputting a new vertical address after each successive addition until said first vertical address equals a second vertical address.
 23. The invention of claim 22 wherein said means for calculating horizontal address values comprises:first horizontal address summing means for adding two horizontal addresses input from said data memory means; first divider means for dividing the sum of said horizontal addresses to yield a span horizontal midpoint address; second horizontal summing means for adding a first horizontal address from said data memory means and said horizontal midpoint address; second divider means for dividing the sum of said first horizontal address and said horizontal midpoint address to yield a one-fourth span horizontal address; third horizontal summing means for adding a second horizontal address from said data memory means and said horizontal midpoint address; and third divider means for dividing the sum of said second horizontal address and said horizontal midpoint address to yield a three-fourths span horizontal address.
 24. In a computer image generating system for generating an image of an object from stored data by color intensity control of a plurality of pixels forming the image of the object, the color intensity for each pixel being derived from a plurality of cells each having a predetermined color intensity value and a predetermined center position, and further a grouping of cells defining a texture pattern formed on a surface of the object, a method for determining color intensity for the plurality of pixels while obtaining smooth transitions between cell boundaries, the method comprising the steps of:(a) defining a location of a pixel to be displayed; (b) identifying the cells about a projection of the pixel whose centers define the corners of a polygon containing the center of the projection of the pixel; (c) determining the location of the projection of the pixel center with respect to each cell identified in step (b); (d) forming a weighted average value of color intensity for the pixel as a function of each cell color intensity value for cells identified in step (b) and the respective location determined in step (c); and (e) providing the weighted average value determined in step (d) for color intensity control of the pixel.
 25. The method of claim 24 including the further steps of:(f) storing a translucency value for each cell; (g) determining a translucency mask having a predetermined number of subpixels for the pixel to be displayed; and (h) modifying the weighted average color intensity value in response to the translucency mask, wherein the modified weighted average color intensity value is supplied for color intenity control of the pixel.
 26. The method of claim 24 and including the further steps of:computing an apparent distance from a viewer to the object; and filtering the cell data to selectively reduce the level of detail of the object as the apparent distance increases.
 27. The method of claim 26 and including the step of establishing a plurality of zones of apparent distances between the viewer and the object, the step of filtering occurring at each transition between zones.
 28. The method of claim 24 and including the step of establishing from a single high level of detail image map of the object a plurality of level of detail image maps for a stored image of the object, each subsequent level of detail map being obtained by filering data representative of predetermined ones of the plurality of cells to obtain a filtered color intensity value for a single cell representative of the predetermined ones of the plurality of cells.
 29. The method of claim 24 and including the steps of:determining an apparent distance from a viewer to the object; identifying two consecutive level of detail maps bracketing the determined apparent distance; computing the weighted average value of color intensity for the pixel for each of the two consecutive level of detail maps; and blending the two computed weighted average color intensity values to obtain a blended color intensity value, wherein the blended color intensity value is supplied for color intensity control of the pixel.
 30. The method of claim 29 wherein said step of blending comprises the step of bilinearly interpolating the blended value in proportion to the relation apparent distance from each of the two level of detail maps.
 31. The method of claim 24, wherein a stored image of the object to be displayed is defined by a face having cells defined by the stored data and including the steps of:determining the angle of a view ray from a predetermined view-point to a plane of the face; computing a translucency factor as a function of the determined angle; and modifying the weighted average value in response to the translucency factor thereby gradually to fade out faces oriented edge-on to a viewer.
 32. The method of claim 24 wherein the step of forming a weight average value comprises the step of bilinearly interpolating the respective color intensity value for each cell identified in step (b) in response to the respective distance from each cell center to the projection of the pixel center.
 33. The method of claim 24 wherein the step of identifying cells comprises the step of identifying four adjacent cells whose centers define a polygon containing the center of the projection of the pixel. 